SH7720 Datasheet, PDF (1311/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 37 List of Registers
Register Name
Abbreviation
LCDC data format register
LDDFR
LCDC scan mode register
LDSMR
LCDC data fetch start address
register for upper display panel
LDSARU
LCDC data fetch start address
register for lower display panel
LDSARL
LCDC fetch data line address offset LDLAOR
register for display panel
LCDC palette control register
LDPALCR
LCDC horizontal character number LDHCNR
register
LCDC horizontal synchronization
signal register
LDHSYNR
LCDC vertical displayed line number LDVDLNR
register
LCDC vertical total line number
register
LDVTLNR
LCDC vertical synchronization signal LDVSYNR
register
LCDC AC modulation signal toggle LDACLNR
line number register
LCDC interrupt control register
LDINTR
LCDC power management mode
register
LDPMMR
LCDC power supply sequence
period register
LDPSPR
LCDC control register
LDCNTR
LCDC user specified interrupt
control register
LDUINTR
LCDC user specified interrupt line LDUINTLNR
number register
LCDC memory access interval
number register
LDLIRNR
Number
of Bits Address
16
H'A440 0404
16
H'A440 0406
32
H'A440 0408
32
H'A440 040C
16
H'A440 0410
16
H'A440 0412
16
H'A440 0414
16
H'A440 0416
16
H'A440 0418
16
H'A440 041A
16
H'A440 041C
16
H'A440 041E
16
H'A440 0420
16
H'A440 0424
16
H'A440 0426
16
H'A440 0428
16
H'A440 0434
16
H'A440 0436
16
H'A440 0440
Module
LCDC
Access
Size
16
16
32
32
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Rev. 3.00 Jan. 18, 2008 Page 1249 of 1458
REJ09B0033-0300