SH7720 Datasheet, PDF (1467/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
9.4.2 CSn Space Bus Control
Register (CSnBCR)
Page Revision (See Manual for Details)
294 Changed
Bit Bit Name Description
30 IWW2
29 IWW1
28 IWW0
Idle Cycles between Write-Read Cycles
and Write-Write Cycles
…
000: No idle cycle
…
9.4.3 CSn Space Wait Control
Register (CSnWCR)
(1) Normal Space, Byte-Selection
SRAM
• CS0WCR, CS6BWCR
• CS2WCR, CS3WCR
• CS4WCR
• CS5AWCR
• CS5BWCR
• CS6AWCR
• CS4WCR
• CS5AWCR
• CS5BWCR
Added
Bit R/W
10 R/W
9 R/W
8 R/W
7 R/W
Description
…
Specify the number of wait cycles that are
necessary for read or write access.
…
Added
Bit Bit Name Description
18 R/W
…
17 R/W
16 R/W
Specify the number of cycles that are
necessary for write access.
000: The same cycles as WR3 to WR0
setting (read or write access wait)
Rev. 3.00 Jan. 18, 2008 Page 1405 of 1458
REJ09B0033-0300