SH7720 Datasheet, PDF (459/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
(2) Basic Timing for I/O Card Interface
Figures 9.41 and 9.42 show the basic timings for the PCMCIA I/O card interface.
The I/O card and IC memory card interfaces can be switched using an address to be accessed. If
area 5 of the physical space is specified as the PCMCIA, the I/O card interface can automatically
be accessed by accessing the physical addresses from H'16000000 to H'17FFFFFF. If area 6 of the
physical space is specified as the PCMCIA, the I/O card interface can automatically be accessed
by accessing the physical addresses from H'1A000000 to H'1BFFFFFF.
Note that areas to be accessed as the PCMCIA I/O card must be non-cached if they are virtual
space (space P2 or P3) areas, or a non-cached area specified by the MMU.
If the PCMCIA card is accessed as an I/O card in little endian mode, dynamic bus sizing for the
I/O bus can be achieved using the IOIS16 signal. If the IOIS16 signal is brought high in a word-
size I/O bus cycle while the bus width of area 6 is specified as 16 bits, the bus width is recognized
as 8 bits and data is accessed twice in 8-bit units in the I/O bus cycle to be executed.
The IOIS16 signal is sampled at the falling edge of CKIO in the Tpci0, Tpci0w, and Tpci1 cycles
when the TED[3:0] bits are specified as 1.5 cycles or more, and is reflected in the CE2 signal 1.5
cycles after the CKIO sampling point. The TED[3:0] bits must be specified appropriately to satisfy
the setup time from ICIORD and ICIOWR of the PC card to CEn.
Figure 9.43 shows the dynamic bus sizing basic timing.
Note that the IOIS16 signal is not supported in big endian mode. In the big endian mode, the
IOIS16 signal must be fixed low.
Rev. 3.00 Jan. 18, 2008 Page 397 of 1458
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