SH7720 Datasheet, PDF (1175/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 33 User Break Controller (UBC)
33.2 Register Descriptions
The user break controller has the following registers. Refer to section 37, List of Registers, for
more details on the addresses and access size of these registers.
• Break address register A (BARA)
• Break address mask register A (BAMRA)
• Break bus cycle register A (BBRA)
• Break address register B (BARB)
• Break address mask register B (BAMRB)
• Break bus cycle register B (BBRB)
• Break data register B (BDRB)
• Break data mask register B (BDMRB)
• Break control register (BRCR)
• Execution times break register (BETR)
• Branch source register (BRSR)
• Branch destination register (BRDR)
• Break ASID register A (BASRA)
• Break ASID register B (BASRB)
33.2.1 Break Address Register A (BARA)
BARA is a 32-bit readable/writable register. BARA specifies the address used as a break condition
in channel A.
Initial
Bit
Bit Name Value R/W Description
31 to 0 BAA31 to All 0
BAA0
R/W Break Address A
Store the address on the LAB or IAB specifying break
conditions of channel A.
Rev. 3.00 Jan. 18, 2008 Page 1113 of 1458
REJ09B0033-0300