SH7720 Datasheet, PDF (375/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
Bit
6
5 to 0
Initial
Bit Name Value R/W Description
WM
0
R/W External Wait Mask Specification
Specify whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycles is 0.
0: External wait is valid
1: External wait is ignored

All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
• CS4WCR
Initial
Bit
Bit Name Value
31 to 21 
All 0
20
BEN
0
19, 18 
All 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Burst Enable Specification
Enables or disables 8-burst access for a 16-bit bus width or
16- burst access for an 8-bit bus width during 16-byte access.
If this bit is set to 1, 2-burst access is performed four times
when the bus width is 16 bits and 4-burst access is
performed four times when the bus width is 8 bits.
To use a device that does not support 8-burst access or 16-
burst access, set this bit to 1.
0: Enables 8-burst access for a 16-bit bus width and 16-burst
access for an 8-bit bus width.
1: Disables 8-burst access for a 16-bit bus width and 16-burst
access for an 8-bit bus width.
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 313 of 1458
REJ09B0033-0300