SH7720 Datasheet, PDF (674/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
18.3.11 FIFO Data Count Register (SCFDR)
SCFDR is a 16-bit register which indicates the number of data stored in the receive FIFO data
register (SCFRDR). The SCFDR is always read from the CPU.
The bits 14 to 8 of this register indicate the number of transmit data items stored in the SCFTDR
that have not yet been transmitted.
The bits 6 to 0 of this register indicate the number of receive data items stored in the SCFRDR.
Bit Bit Name Initial Value R/W
15 —
0
R
14 T6
0
R
13 T5
0
R
12 T4
0
R
11 T3
0
R
10 T2
0
R
9
T1
0
R
8
T0
0
R
7
—
0
R
6
R6
0
R
5
R5
0
R
4
R4
0
R
3
R3
0
R
2
R2
0
R
1
R1
0
R
0
R0
0
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
These bits indicate the number of non-transmitted
data stored in the SCFTDR. The H'00 means no
transmit data, and the H'40 means that the full of
transmit data are stored in the SCFTDR.
Reserved
This bit is always read as 0. The write value should
always be 0.
These bits indicate the number of receive data
stored in the SCFRDR. The H'00 means no receive
data, and the H'40 means that the full of receive
data are stored in the SCFRDR.
Rev. 3.00 Jan. 18, 2008 Page 612 of 1458
REJ09B0033-0300