SH7720 Datasheet, PDF (1462/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
Page Revision (See Manual for Details)
8.3.1 Interrupt Priority Registers A 248
to J (IPRA to IPRJ)
Table 8.2 Interrupt Sources and
IPRA to IPRJ
Amended
Register Bits 15 to 12
IPRD
Reserved*
IPRG
SCIF0
Bits 7 to 4
IRQ5
Reserved*
Bits 3 to 0
IRQ4
Reserved*
IPRJ
Reserved*
SDHI
AFEIF
Note: * Reserved. Always read as 0. The write value
should always be 0. The SSL and SDHI -related
bits are effective only for the models that include
them. Reserved bits apply if they are not included.
8.3.4 Interrupt Request Register 0 252
(IRR0)
Changed
IRR0 is an 8-bit register that indicates interrupt
requests from the TMU and IRQ0 to IRQ5.
Initial
Bit Bit Name Value
7
0
R/W Description
R Reserved
This bit is always read as
0. The write value should
always be 0.
8.3.5 Interrupt Request Register 1 253
(IRR1)
8.3.6 Interrupt Request Register 2 254
(IRR2)
Deleted
IRR1 is an 8-bit register that indicates whether interrupt
requests from the DMAC and LCDC are generated.
Changed
IRR2 is an 8-bit register that indicates whether interrupt
requests from the SSL and LCDC are generated. This
register is initialized to H'00 by a power-on reset or
manual reset, but is not initialized in standby mode.
Note: On the models not having the SSL, the SSL-
related bits are reserved. The write value should always
be 0.
Added
Bit Bit Name Description
4 SSLIR SSLI Interrupt Request
…
Note: On the models not having the
SSL, this bit is reserved and always read
as 0. The write value should always be 0.
Rev. 3.00 Jan. 18, 2008 Page 1400 of 1458
REJ09B0033-0300