SH7720 Datasheet, PDF (131/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Table 2.7 Arithmetic Operation Instructions
Instruction
Instruction Code Operation
Privileged
Mode
Cycles T Bit
ADD
Rm,Rn 0011nnnnmmmm1100 Rn+Rm→Rn
–
1
–
ADD
#imm,Rn 0111nnnniiiiiiii
Rn+imm→Rn
–
1
–
ADDC
Rm,Rn 0011nnnnmmmm1110 Rn+Rm+T→Rn, Carry→T
–
1
Carry
ADDV
Rm,Rn 0011nnnnmmmm1111 Rn+Rm→Rn, Overflow→T
–
1
Overflow
CMP/EQ #imm,R0 10001000iiiiiiii
If R0 = imm, 1 → T
–
1
Comparison
result
CMP/EQ Rm,Rn 0011nnnnmmmm0000 If Rn = Rm, 1 → T
–
1
Comparison
result
CMP/HS Rm,Rn
0011nnnnmmmm0010 If Rn ≥ Rm with unsigned data, –
1→T
1
Comparison
result
CMP/GE Rm,Rn 0011nnnnmmmm0011 If Rn ≥ Rm with signed data, –
1→T
1
Comparison
result
CMP/HI Rm,Rn
0011nnnnmmmm0110 If Rn > Rm with unsigned data, –
1→T
1
Comparison
result
CMP/GT Rm,Rn
0011nnnnmmmm0111 If Rn > Rm with signed data, –
1→T
1
Comparison
result
CMP/PL Rn
0100nnnn00010101 If Rn ≥ 0, 1 → T
–
1
Comparison
result
CMP/PZ Rn
0100nnnn00010001 If Rn > 0, 1 → T
–
1
Comparison
result
CMP/STR Rm,Rn 0010nnnnmmmm1100 If Rn and Rm have an
–
equivalent byte, 1 → T
1
Comparison
result
DIV1
Rm,Rn 0011nnnnmmmm0100 Single-step division (Rn/Rm) –
1
Calculatio
n result
DIV0S
Rm,Rn
0010nnnnmmmm0111 MSB of Rn → Q,
–
MSB of Rm → M, M ^ Q → T
1
Calculatio
n result
DIV0U
0000000000011001 0 → M/Q/T
–
1
0
DMULS.L Rm,Rn
0011nnnnmmmm1101 Signed operation of Rn × Rm –
→ MACH,
MACL 32 × 32 → 64 bits
2 (to –
5)*
DMULU.L Rm,Rn 0011nnnnmmmm0101 Unsigned operation of Rn × –
Rm → MACH,
MACL 32 × 32 → 64 bits
2 (to –
5)*
DT
Rn
0100nnnn00010000 Rn – 1 → Rn,
–
if Rn = 0, 1 → T, else 0 → T
1
Comparison
result
Rev. 3.00 Jan. 18, 2008 Page 69 of 1458
REJ09B0033-0300