SH7720 Datasheet, PDF (660/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name Initial Value R/W Description
4
RE
0
R/W Receive Enable
Enables or disables the SCIF serial receiver.
0: Receiver disabled*¹
1: Receiver enabled*²
Notes: 1. Clearing RE to 0 does not affect the receive
flags (DR, ER, BRK, RDF, FER, PER, and
ORER). These flags retain their previous
values.
2. The serial mode register (SCSMR) and FIFO
control register (SCFCR) should be set to
select the receive format and reset the receive
FIFO before setting the RE bit to 1.
3, 2 —
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
1
CKE1 0
R/W Clock Enable 1and 0
0
CKE0 0
R/W These bits select the SCIF clock source. The bits CKE1
and CKE0 should be set before selecting the SCIF
operating mode by SCSMR.
00: Internal clock, SCK pin used for input pin (input signal
is ignored)*¹
01: Internal clock, SCK pin used for synchronous clock
output*²
10: External clock, SCK pin used for clock input*³
11: External clock, SCK pin used for clock input*³
Notes: 1. When the data sampling is executed using on-
chip baud rate generator, CKE1 and CKE0
should be set to 00.
2. In synchronous mode, a clock with a
frequency equal to the bit rate is output. When
the channel 0 is used as the IrDA interface,
CKE1 and CKE0 should be set to 01.
3. In asynchronous mode, input the clock which
is appropriate for the sampling rate. For
example, when the sampling rate is 1/16,
input the clock frequency 8 times the bit rate.
When the external clock is not input, CKE1
and CKE0 should be set to 00.
When the SCK pin is set as an I/O port pin,
CKE1 and CKE0 should be set to 00.
Rev. 3.00 Jan. 18, 2008 Page 598 of 1458
REJ09B0033-0300