SH7720 Datasheet, PDF (748/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
21.3.2 Control Register (SICTR)
SICTR is a 16-bit readable/writable register that sets the SIOF operating state.
Initial
Bit
Bit Name Value R/W Description
15
SCKE
0
R/W Serial Clock Output Enable
This bit is valid in master mode.
0: Disables the SIOFSCK output (outputs 0)
1: Enables the SIOFSCK output
• If this bit is set to 1, the SIOF initializes the baud
rate generator and initiates the operation. At the
same time, the SIOF outputs the clock generated by
the baud rate generator to the SIOFSCK pin.
This bit is initialized in module stop mode.
14
FSE
0
R/W Frame Synchronous Signal Output Enable
This bit is valid in master mode.
0: Disables the SIOFSYNC output (outputs 0)
1: Enables the SIOFSYNC output
• If this bit is set to 1, the SIOF initializes the frame
counter and initiates the operation.
This bit is initialized in module stop mode.
13 to 10 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 686 of 1458
REJ09B0033-0300