SH7720 Datasheet, PDF (613/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Compare Match Timer (CMT)
16.2.2 Compare Match Timer Control/Status Register (CMCSR)
CMCSR is a 16-bit register that indicates the occurrence of compare matches, enables interrupts
and DMA transfer request, and sets the counter input clocks.
Do not change bits other than bits CMF and OVF during the compare match timer counter
(CMCNT) operation.
Initial
Bit
Bit Name Value
15
CMF
0
14
OVF
0
13 to 10 
All 0
R/W Description
R/(W)*¹ Compare Match Flag
This flag indicates whether or not values of the compare
match timer counter (CMCNT) and compare match timer
constant register (CMCOR) have matched.
Software cannot write 1 to the bit. When one-shot is
selected for the counter operation, counting resumes by
clearing this bit.
0: CMCNT and CMCOR values have not matched
[Clearing condition]
• Write 0 to CMF after reading CMF=1
1: CMCNT and CMCOR values have matched
R/(W)*¹ Overflow Flag
This flag indicates whether or not the compare match
timer counter (CMCNT) has overflowed and been cleared
to 0. Software cannot write 1 to this bit.
0: CMCNT has not overflowed
[Clearing condition]
• Write 0 to OVF after reading OVF=1
1: CMCNT has overflowed
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 551 of 1458
REJ09B0033-0300