SH7720 Datasheet, PDF (316/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
8.3.6 Interrupt Request Register 2 (IRR2)
IRR2 is an 8-bit register that indicates whether interrupt requests from the SSL and LCDC are
generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not
initialized in standby mode.
Note: On the models not having the SSL, the SSL-related bits are reserved. The write value
should always be 0.
Bit
7 to 5
Bit Name

4
SSLIR
3 to 1 
0
LCDIR
Initial Value R/W
All 0
R
0
R/W
All 0
R
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
SSLI Interrupt Request
Indicates whether the SSLI (SSL) interrupt
request is generated.
0: SSLI interrupt request is not generated
1: SSLI interrupt request is generated
Note: On the models not having the SSL, this bit
is reserved and always read as 0. The write
value should always be 0.
Reserved
These bits are always read as 0. The write value
should always be 0.
LCDCI Interrupt Request
Indicates whether the LCDCI (LCDC) interrupt
request is generated.
0: LCDCI interrupt request is not generated
1: LCDCI interrupt request is generated
Rev. 3.00 Jan. 18, 2008 Page 254 of 1458
REJ09B0033-0300