SH7720 Datasheet, PDF (1002/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 27 A/D Converter
27.4.3 Scan Mode
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit in the A/D control/status register (ADCSR) is set to 1 by software, A/D conversion
starts on the first channel (AN0). When two or more channels are selected, after conversion of the
first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion
continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion
results are transferred for storage into the A/D data registers corresponding to the channels.
When the mode or analog input channel must be changed during analog conversion, to prevent
incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the
necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in
the group. The ADST bit can be set at the same time as the mode or channel selection is changed.
Typical operations when three channels (AN0 to AN2) are selected in scan mode are described
next. Figure 27.4 shows a timing diagram for this example.
1. Start the clock supply to the ADC module (clear the MSTP33 bit in STBCR3 to 0) to run the
ADC module.
2. Scan mode is selected, analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0),
and A/D conversion is started (ADST = 1).
3. When A/D conversion of the first channel (AN0) is completed, the result is transferred into
ADDRA.
4. Next, conversion of the second channel (AN1) starts automatically.
5. Conversion proceeds in the same way through the third channel (AN2).
6. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set
to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI
interrupt is requested at this time.
7. Steps 3 to 5 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops.
8. Stop the clock supply to the ADC module (set the MSTP33 bit in STBCR3 to 1) to place the
ADC in the module standby state.
Rev. 3.00 Jan. 18, 2008 Page 940 of 1458
REJ09B0033-0300