SH7720 Datasheet, PDF (129/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Table 2.6 Data Transfer Instructions
Instruction
MOV #imm,Rn
MOV.W @(disp,PC),Rn
MOV.L @(disp,PC),Rn
MOV Rm,Rn
MOV.B Rm,@Rn
MOV.W Rm,@Rn
MOV.L Rm,@Rn
MOV.B @Rm,Rn
MOV.W @Rm,Rn
MOV.L @Rm,Rn
MOV.B Rm,@–Rn
MOV.W Rm,@–Rn
MOV.L Rm,@–Rn
MOV.B @Rm+,Rn
MOV.W @Rm+,Rn
MOV.L @Rm+,Rn
MOV.B R0,@(disp,Rn)
MOV.W R0,@(disp,Rn)
MOV.L Rm,@(disp,Rn)
MOV.B @(disp,Rm),R0
MOV.W @(disp,Rm),R0
MOV.L @(disp,Rm),Rn
MOV.B Rm,@(R0,Rn)
MOV.W Rm,@(R0,Rn)
MOV.L Rm,@(R0,Rn)
Instruction Code Operation
Privileged
Mode
Cycles T Bit
1110nnnniiiiiiii
imm → Sign extension → Rn –
1
–
1001nnnndddddddd (disp x 2+PC)→Sign
–
extension → Rn
1
–
1101nnnndddddddd (disp x 4+PC)→Rn
–
1
–
0110nnnnmmmm0011 Rm→Rn
–
1
–
0010nnnnmmmm0000 Rm→(Rn)
–
1
–
0010nnnnmmmm0001 Rm→(Rn)
–
1
–
0010nnnnmmmm0010 Rm→(Rn)
–
1
–
0110nnnnmmmm0000 (Rm)→Sign extension→Rn –
1
–
0110nnnnmmmm0001 (Rm)→Sign extension→Rn –
1
–
0110nnnnmmmm0010 (Rm)→Rn
–
1
–
0010nnnnmmmm0100 Rn–1→Rn, Rm→(Rn)
–
1
–
0010nnnnmmmm0101 Rn–2→Rn, Rm→(Rn)
–
1
–
0010nnnnmmmm0110 Rn–4→Rn, Rm→(Rn)
–
1
–
0110nnnnmmmm0100 (Rm)→Sign extension→Rn, –
Rm+1→Rm
1
–
0110nnnnmmmm0101 (Rm)→Sign extension→Rn, –
Rm+2→Rm
1
–
0110nnnnmmmm0110 (Rm)→Rn, Rm+4→Rm
–
1
–
10000000nnnndddd R0→(disp+Rn)
–
1
–
10000001nnnndddd R0→(disp x 2+Rn)
–
1
–
0001nnnnmmmmdddd Rm→(disp x 4+Rn)
–
1
–
10000100mmmmdddd (disp+Rm)→Sign
extension→R0
–
1
–
10000101mmmmdddd (disp x 2+Rm)→Sign
–
extension→R0
1
–
0101nnnnmmmmdddd (disp x 4+Rm)→Rn
–
1
–
0000nnnnmmmm0100 Rm→(R0+Rn)
–
1
–
0000nnnnmmmm0101 Rm→(R0+Rn)
–
1
–
0000nnnnmmmm0110 Rm→(R0+Rn)
–
1
–
Rev. 3.00 Jan. 18, 2008 Page 67 of 1458
REJ09B0033-0300