SH7720 Datasheet, PDF (137/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Instruction
Instruction Code Operation
LDC.L @Rm+,
R5_BANK
0100mmmm11010111 (Rm)→R5_BANK, Rm+4→Rm
LDC.L @Rm+,
R6_BANK
0100mmmm11100111 (Rm)→R6_BANK, Rm+4→Rm
LDC.L @Rm+,
R7_BANK
0100mmmm11110111 (Rm)→R7_BANK, Rm+4→Rm
LDS Rm,MACH
0100mmmm00001010 Rm→MACH
LDS Rm,MACL
0100mmmm00011010 Rm→MACL
LDS Rm,PR
0100mmmm00101010 Rm→PR
LDS.L @Rm+,MACH 0100mmmm00000110 (Rm)→MACH, Rm+4→Rm
LDS.L @Rm+,MACL 0100mmmm00010110 (Rm)→MACL, Rm+4→Rm
LDS.L @Rm+,PR 0100mmmm00100110 (Rm)→PR, Rm+4→Rm
LDTLB
0000000000111000 PTEH/PTEL→TLB
NOP
0000000000001001 No operation
PREF @Rm
0000mmmm10000011 (Rm) → cache
RTE
0000000000101011
Delayed branch, SSR → SR,
SPC → PC
SETS
0000000001011000 1→S
SETT
0000000000011000 1→T
SLEEP
0000000000011011 Sleep
STC SR,Rn
0000nnnn00000010 SR→Rn
STC GBR,Rn
0000nnnn00010010 GBR→Rn
STC VBR,Rn
0000nnnn00100010 VBR→Rn
STC SSR, Rn
0000nnnn00110010 SSR→Rn
STC SPC,Rn
0000nnnn01000010 SPC→Rn
STC R0_BANK,Rn 0000nnnn10000010 R0_BANK→Rn
STC R1_BANK,Rn 0000nnnn10010010 R1_BANK→Rn
STC R2_BANK,Rn 0000nnnn10100010 R2_BANK→Rn
STC R3_BANK,Rn 0000nnnn10110010 R3_BANK→Rn
STC R4_BANK,Rn 0000nnnn11000010 R4_BANK→Rn
STC R5_BANK,Rn 0000nnnn11010010 R5_BANK→Rn
STC R6_BANK,Rn 0000nnnn11100010 R6_BANK→Rn
Privileged
Mode
Cycles T Bit
√
4
–
√
4
–
√
4
–
–
1
–
–
1
–
–
1
–
–
1
–
–
1
–
–
1
–
√
1
–
–
1
–
–
1
–
√
5
–
–
1
–
–
1
1
√
4*¹
–
√
1
–
–
1
–
√
1
–
√
1
–
√
1
–
√
1
–
√
1
–
√
1
–
√
1
–
√
1
–
√
1
–
√
1
–
Rev. 3.00 Jan. 18, 2008 Page 75 of 1458
REJ09B0033-0300