SH7720 Datasheet, PDF (598/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 15 16-Bit Timer Pulse Unit (TPU)
TCNT value
TGRB
TGRA
H'0000
N (A)
TGRC N (A)
N (B)
TGRA
N (A)
N (B)
N (TGRB+1)
N (B)
N (TGRB+1)
Time
N (TGRB+1)
TPU_TO pin
Figure 15.10 Example of Buffer Operation
15.4.4 PWM Modes
In PWM mode, PWM waveforms are output from the output pins. 0, or 1, output can be selected
as the output level in response to compare match of each TGRA.
Designating TGRB compare match as the counter clearing source enables the period to be set in
that register. All channels can be designated for PWM mode independently.
PWM output is generated from the TPU_TO pin using TGRB as the period register and TGRA as
duty registers. The output specified in TIOR is performed by means of compare matches. Upon
counter clearing by a period register compare match, the output value of each pin is the initial
value set in TIOR. Set TIOR so that the initial output and an output value by compare match are
different. If the same levels or toggle outputs are selected, operation is disabled.
Conditions of duty 0% and 100% are shown below.
• Duty 0%: The set value of the duty register (TGRA) is TGRB + 1 for the period
register(TGRB).
• Duty 100%: The set value of the duty register (TGRA) is 0.
In PWM mode 1, a maximum 4-phase PWM output is possible.
Rev. 3.00 Jan. 18, 2008 Page 536 of 1458
REJ09B0033-0300