SH7720 Datasheet, PDF (510/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 10 Direct Memory Access Controller (DMAC)
10.5 Usage Notes
Pay attentions to the following notes when the DMAC is used.
10.5.1 Notes on DACK Pin Output
When burst mode and cycle steal mode are simultaneously set in two or more channels, an
additional DACK may be asserted at the end of burst transfer. This phenomenon will occur when
all of the conditions described below are satisfied.
1. When the DMA transfer is simultaneously performed in two or more channels support both
burst mode and cycle steal mode
2. When the channel to be used in burst mode is set to dual address mode, and DACK is output in
data write cycle
3. When the DMAC cannot obtain the bus mastership consecutively even though a transfer
demand of cycle steal has been received after the completion of burst transfer
This phenomenon is avoided by taking either of three measures shown below.
• Measure 1
After confirming the completion of burst transfer (TE bit = 1), perform the DMA transfer of
other cycle steal mode
• Measure 2
The channel to be used in burst mode should not be set to output DACK in data write cycle
• Measure 3
When the DMA transfer is simultaneously performed in two or more channels, set all of the
channels to burst mode or cycle steal mode
10.5.2 Notes on the Cases When DACK is Divided
(1) Overview
When DACK is divided for output while the DMAC is accessing an external device, sampling of
DREQ may be accepted once more during the access.
(2) Conditions and Phenomena
Conditions: In the cases when DACK is divided for output during external access, specifically, the
following cases:
Rev. 3.00 Jan. 18, 2008 Page 448 of 1458
REJ09B0033-0300