SH7720 Datasheet, PDF (178/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
Table 3.16 DSR Register Bits
Initial
Bits Bit Name Value R/W
31 to 8 
All 0
R
7
GT
0
R/W
6
Z
0
R/W
5
N
0
R/W
4
V
0
R/W
Function
Reserved
These bits are always read as 0. The write value should
always be 0.
Signed Greater Bit
Indicates that the operation result is positive (except 0),
or that operand 1 is greater than operand 2
1: Operation result is positive, or operand 1 is greater
than operand 2
Zero Bit
Indicates that the operation result is zero (0), or that
operand 1 is equal to operand 2
1: Operation result is zero (0), or operands are equal
Negative Bit
Indicates that the operation result is negative, or that
operand 1 is smaller than operand 2
1: Operation result is negative, or operand 1 is smaller
than operand 2
Overflow Bit
Indicates that the operation result has overflowed
1: Operation result has overflowed
Rev. 3.00 Jan. 18, 2008 Page 116 of 1458
REJ09B0033-0300