SH7720 Datasheet, PDF (123/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Instruction Format
nm type
15
0
xxxx nnnn mmmm xxxx
md type
15
0
xxxx xxxx mmmm dddd
nd4 type
15
0
xxxx xxxx nnnn dddd
nmd type
15
0
xxxx nnnn mmmm dddd
Section 2 CPU
Source Operand
mmmm: register
direct
Destination
Operand
nnnn: register
direct
Sample Instruction
ADD Rm,Rn
mmmm: register nnnn: register
indirect
indirect
MOV.L Rm,@Rn
mmmm: post-
increment register
indirect (multiply-
and-accumulate
operation)
MACH, MACL
MAC.W @Rm+,@Rn+
nnnn: * post-
increment register
indirect (multiply-
and-accumulate
operation)
mmmm: post-
nnnn: register
increment register direct
indirect
MOV.L @Rm+,Rn
mmmm: register
direct
nnnn: pre-
MOV.L Rm,@-Rn
decrement register
indirect
mmmm: register nnnn: indexed
direct
register indirect
MOV.L Rm,@(R0,Rn)
mmmmdddd:
R0 (register direct) MOV.B @(disp,Rm),R0
register indirect
with displacement
R0 (register direct) nnnndddd:
MOV.B R0,@(disp,Rn)
register indirect
with displacement
mmmm: register
direct
nnnndddd:
MOV.L Rm,@(disp,Rn)
register indirect
with displacement
mmmmdddd:
nnnn: register
register indirect direct
with displacement
MOV.L @(disp,Rm),Rn
Rev. 3.00 Jan. 18, 2008 Page 61 of 1458
REJ09B0033-0300