SH7720 Datasheet, PDF (717/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 20 I²C Bus Interface (IIC)
20.3.5 I²C Bus Status Register (ICSR)
ICSR performs confirmation of interrupt request flags and status.
Initial
Bit
Bit Name Value R/W Description
7
TDRE
0
R/W Transmit Data Register Empty
[Setting condition]
• When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
• When TRS is set
• When a start condition (including re-transfer) has
been issued
• When transmit mode is entered from receive mode in
slave mode
[Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When data is written to ICDRT with an instruction
6
TEND
0
R/W Transmit End
[Setting conditions]
• When the ninth clock of SCL rises with the I²C bus
format while the TDRE flag is 1
[Clearing conditions]
• When 0 is written in TEND after reading TEND = 1
• When data is written to ICDRT with an instruction
5
RDRF
0
R/W Receive Data Register Full
[Setting condition]
• When a receive data is transferred from ICDRS to
ICDRR
[Clearing conditions]
• When 0 is written in RDRF after reading RDRF = 1
• When ICDRR is read with an instruction
Rev. 3.00 Jan. 18, 2008 Page 655 of 1458
REJ09B0033-0300