SH7720 Datasheet, PDF (211/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

3.6 DSP Extended Function Instruction Set
Section 3 DSP Operating Unit
3.6.1 CPU Extended Instructions
Table 3.35 DSP Mode Extended System Control Instructions
Instruction
SETRC #imm
SETRC Rn
LDRS @(disp,PC)
LDRE @(disp,PC)
STC MOD,Rn
STC RS,Rn
STC RE,Rn
STS DSR,Rn
STS A0,Rn
STS X0,Rn
STS X1,Rn
STS Y0,Rn
STS Y1,Rn
STS.L DSR,@-Rn
STS.L A0,@-Rn
STS.L X0,@-Rn
STS.L X1,@-Rn
STS.L Y0,@-Rn
STS.L Y1,@-Rn
STC.L MOD,@-Rn
STC.L RS,@-Rn
STC.L RE,@-Rn
LDS.L @Rn + ,DSR
LDS.L @Rn + ,A0
LDS.L @Rn + ,X0
LDS.L @Rn + ,X1
LDS.L @Rn + ,Y0
Instruction Code
10000010iiiiiiii
0100nnnn00010100
10001100dddddddd
10001110dddddddd
0000nnnn01010010
0000nnnn01100010
0000nnnn01110010
0000nnnn01101010
0000nnnn01111010
0000nnnn10001010
0000nnnn10011010
0000nnnn10101010
0000nnnn10111010
0100nnnn01100010
0100nnnn01110010
0100nnnn10000010
0100nnnn10010010
0100nnnn10100010
0100nnnn10110010
0100nnnn01010011
0100nnnn01100011
0100nnnn01110011
0100nnnn01100110
0100nnnn01110110
0100nnnn10000110
0100nnnn10010110
0100nnnn10100110
Operation
Execution States T Bit
imm → RC (of SR)
1
–
Rn[11:0] → RC(of SR) 1
–
(disp x 2 + PC) → RS
1
–
(disp x 2 + PC) → RE
1
–
MOD →Rn
1
–
RS → Rn
1
–
RE → Rn
1
–
DSR → Rn
1
–
A0 → Rn
1
–
X0 → Rn
1
–
X1 → Rn
1
–
Y0 → Rn
1
–
Y1 → Rn
1
–
Rn-4 → Rn, DSR → (Rn) 1
–
Rn-4 → Rn, A0 → (Rn) 1
–
Rn-4 → Rn, X0 → (Rn) 1
–
Rn-4 → Rn, X1 → (Rn) 1
–
Rn-4 → Rn, Y0 → (Rn) 1
–
Rn-4 → Rn, Y1 →(Rn) 1
–
Rn-4 → Rn, MOD → (Rn) 1
–
Rn-4 → Rn, RS → (Rn) 1
–
Rn-4 → Rn, RE → (Rn) 1
–
(Rn) → DSR, Rn + 4→Rn 1
–
(Rn) → A0, Rn + 4 → Rn 1
–
(Rn) → X0, Rn + 4 → Rn 1
–
(Rn) → X1, Rn + 4 → Rn 1
–
(Rn) → Y0, Rn + 4 → Rn 1
–
Rev. 3.00 Jan. 18, 2008 Page 149 of 1458
REJ09B0033-0300