SH7720 Datasheet, PDF (36/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Figure 3.22 Local Data Move Instruction Flow.......................................................................... 147
Section 4 Memory Management Unit (MMU)
Figure 4.1 MMU Functions ........................................................................................................ 167
Figure 4.2 Virtual Address Space (MMUCR.AT = 1)................................................................ 169
Figure 4.3 Virtual Address Space (MMUCR.AT = 0)................................................................ 170
Figure 4.4 P4 Area...................................................................................................................... 171
Figure 4.5 Physical Address Space............................................................................................. 172
Figure 4.6 Overall Configuration of the TLB............................................................................. 177
Figure 4.7 Virtual address and TLB Structure............................................................................ 178
Figure 4.8 TLB Indexing (IX = 1) .............................................................................................. 179
Figure 4.9 TLB Indexing (IX = 0) .............................................................................................. 180
Figure 4.10 Objects of Address Comparison.............................................................................. 181
Figure 4.11 Operation of LDTLB Instruction............................................................................. 185
Figure 4.12 Synonym Problem (32-kbyte Cache) ...................................................................... 187
Figure 4.13 MMU Exception Generation Flowchart .................................................................. 193
Figure 4.14 Specifying Address and Data for Memory-Mapped TLB Access ........................... 195
Section 5 Cache
Figure 5.1 Cache Structure ......................................................................................................... 198
Figure 5.2 Cache Search Scheme ............................................................................................... 206
Figure 5.3 Write-Back Buffer Configuration.............................................................................. 208
Figure 5.4 Specifying Address and Data for Memory-Mapped Cache Access
(16-kbyte mode) ........................................................................................................ 211
Section 7 Exception Handling
Figure 7.1 Register Bit Configuration ........................................................................................ 218
Section 8 Interrupt Controller (INTC)
Figure 8.1 Block Diagram of INTC............................................................................................ 244
Figure 8.2 Example of IRL Interrupt Connection....................................................................... 267
Figure 8.3 Interrupt Operation Flowchart................................................................................... 277
Section 9 Bus State Controller (BSC)
Figure 9.1 Block Diagram of BSC ............................................................................................. 282
Figure 9.2 Address Space ........................................................................................................... 286
Figure 9.3 Normal Space Basic Access Timing (Access Wait 0)............................................... 337
Figure 9.4 Continuous Access for Normal Space 1, Bus Width = 16 bits, Longword Access,
CSnWCR.WM Bit = 0 (Access Wait = 0, Cycle Wait = 0) ...................................... 339
Rev. 3.00 Jan. 18, 2008 Page xxxvi of lxii