SH7720 Datasheet, PDF (261/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 5 Cache
(3) LRU
With the 4-way set associative system, up to four instructions or data with the same entry address
can be registered in the cache. When an entry is registered, LRU shows which of the four ways it
is recorded in. There are six LRU bits, controlled by hardware. A least-recently-used (LRU)
algorithm is used to select the way.
Six LRU bits indicate the way to be replaced, when a cache miss occurs. Table 5.2 shows the
relationship between the LRU bits and the way to be replaced when the cache locking mechanism
is disabled. (For the relationship when the cache locking mechanism is enabled, refer to section
5.2.2, Cache Control Register 2 (CCR2).) If a bit pattern other than those listed in table 5.2 is set
in the LRU bits by software, the cache will not function correctly. When modifying the LRU bits
by software, set one of the patterns listed in table 5.2.
The LRU bits are initialized to H'000000 by a power-on reset, but are not initialized by a manual
reset.
Table 5.2 LRU and Way Replacement (when Cache Locking Mechanism is Disabled)
LRU (Bits 5 to 0)
000000, 000100, 010100, 100000, 110000, 110100
000001, 000011, 001011, 100001, 101001, 101011
000110, 000111, 001111, 010110, 011110, 011111
111000, 111001, 111011, 111100, 111110, 111111
Way to be Replaced
3
2
1
0
5.2 Register Descriptions
The cache has the following registers. Refer to section 37, List of Registers, for more details on
the addresses and access size of these registers.
• Cache control register 1 (CCR1)
• Cache control register 2 (CCR2)
• Cache control register 3 (CCR3)
Rev. 3.00 Jan. 18, 2008 Page 199 of 1458
REJ09B0033-0300