SH7720 Datasheet, PDF (808/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 22 Analog Front End Interface (AFEIF)
22.3.6 Ringing Pulse Counter (RCNT)
The result of counting 1 cycle of ringing waveform with AFE_FS is shown here.
Bit
15 to 0
Bit Name
RCNT15 to
RCNT0
Initial Value
All 0
R/W Description
R/W Ringing Counter Value
The result of counting 1 cycle of input ringing
waveform with AFE_FS (output of AFE). See
section 22.4.3, DAA Interface for more detail
about the ringing detect sequence.
22.3.7 AFE Control Data Register (ACDR)
ACDR is the register to store the AFE control word. After 1 is written to HC bit (ACTR1), data is
transferred to AFE at the timing of 3rd FS.
Bit
15 to 0
Bit Name
ACDR15 to
ACDR0
Initial Value R/W Description
All 0
R/W Store the AFE control word.
22.3.8 AFE Status Data Register (ASDR)
ASDR is the register to store the AFE status word. After 1 is written to HC bit (ACTR2), data is
transferred to ASDR from AFE at the timing of 3rd FS.
Bit
15 to 0
Bit Name
ASDR15 to
ASDR0
Initial Value R/W Description
All 0
R Store the AFE control word.
Rev. 3.00 Jan. 18, 2008 Page 746 of 1458
REJ09B0033-0300