SH7720 Datasheet, PDF (835/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 USB Host Controller (USBH)
Initial
Bit
Bit Name Value R/W Description
1
CLF
0
R/W Control List Filled
This bit is used to indicate that there are some TDs in the
control list. This bit is set by HCD when TD is added to ED
in the control list.
When the host controller starts to process the head of the
control list, it checks this bit. As long as this bit is 0, the
host controller does not start to process the control list. If
this bit is 1, the host controller starts to process the control
list and this bit is set to 0. When the host controller finds
TD in the list, the host controller sets this bit to 1. When
TD is never detected in the control list and HCD does not
set this bit, the host controller completes the processing of
the control list. This bit is still 0 when the control list
processing is stopped.
0: The list is not processed
1: The list is processed
0
HCR
0
R/W Host Controller Reset
This bit is set by HCD to initiate the software reset of the
host controller. The system is moved to the UsbSuspend
state in which most of the operational registers are reset
except for the next state regardless of the functional state
of the host controller. For example, an access to the IR bit
in the USBHC register and without host bus is allowed.
The host controller upon completion of the reset operation
clears this bit. This bit does not cause any reset to the
route hub and the next reset signal is not issued to the
downstream port.
0: Cleared by the host controller at the completion of the
reset control
1: UsbSuspend state
Rev. 3.00 Jan. 18, 2008 Page 773 of 1458
REJ09B0033-0300