SH7720 Datasheet, PDF (1099/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 31 MultiMediaCard Interface (MMCIF)
31.3.5 Transfer Block Number Counter (TBNCR)
TBNCR sets the number of blocks to be transferred when multiblock transfer is specified by bits
TY5 and TY6 in CMDTYR. The contents of TBNCR is decremented for every 1-block transfer
completion. When the contents of TBNCR is 0, the command sequence is terminated, and an
interrupt is generated.
Bit Bit Name
15 to 0 TBNCR
Initial
Value
All 0
R/W Description
R/W Transfer Block Number Counter
[Clearing condition]
When the specified number of blocks are transferred and
0 is written to TBNCR.
31.3.6 Command Registers 0 to 5 (CMDR0 to CMDR5)
CMDR are six 8-bit registers. A command is written to CMDR as shown in table 31.3, and a
command is transmitted by setting the START bit in CMDSTRT to 1.
Table 31.3 CMDR Configuration
Register
CMDR0
CMDR1 to CMDR4
CMDR5
Contents
Operation
Start bit, Host bit, and Command index writing
command index
Sets the Start bit to 0, and the Host bit to 1.
Command argument Command argument writing
CRC, End bit
Setting of CRC is unnecessary (automatic
calculation)
Setting of end bit is unnecessary (end bit is set to 1)
• CMDR0
Bit
7
6
5 to 0
Initial
Bit Name Value
Start
0
Host
0
INDEX All 0
R/W Description
R/W Start bit (This bit should be set to 0)
R/W Transmission bit (This bit should be set to 1)
R/W Command indexes
Rev. 3.00 Jan. 18, 2008 Page 1037 of 1458
REJ09B0033-0300