SH7720 Datasheet, PDF (774/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
(2) Transmit/Receive Timing
The SIOFTxD transmit timing and SIOFRxD receive timing relative to the SIOFSCK can be set as
the sampling timing in the following two ways. The transmit/receive timing is set using the REDG
bit in SIMDR.
• Falling-edge sampling
• Rising-edge sampling
Figure 21.4 shows the transmit/receive timing.
(a) Falling-edge sampling
SIOFSCK
(a) Rising-edge sampling
SIOFSCK
SIOFSYNC
SIOFTxD
SIOFRxD
Receive timing
Transmit timing
SIOFSYNC
SIOFTxD
SIOFRxD
Figure 21.4 SIOF Transmit/Receive Timing
Receive timing
Transmit timing
Rev. 3.00 Jan. 18, 2008 Page 712 of 1458
REJ09B0033-0300