SH7720 Datasheet, PDF (1299/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 37 List of Registers
Section 37 List of Registers
The address list gives information on the on-chip I/O registers and is configured as described
below.
1. Register Addresses (by functional module, in order of the corresponding section numbers)
• Descriptions by functional module, in order of the corresponding section numbers
• Access to reserved addresses which are not described in this list is prohibited.
• When registers consist of 16 or 32 bits, the addresses of the MSBs are given, on the
presumption of a big-endian system.
2. Register Bits
• Bit configurations of the registers are described in the same order as the Register Addresses
(by functional module, in order of the corresponding section numbers).
• Reserved bits are indicated by  in the bit name column.
• No entry in the bit-name column indicates that the whole register is allocated as a counter or
for holding data.
• When registers consist of 16 or 32 bits, bits are described from the MSB side.
The order in which bytes are described is on the presumption of a big-endian system.
3. Register States in Each Operating Mode
• Register states are described in the same order as the Register Addresses (by functional
module, in order of the corresponding section numbers).
• For the initial state of each bit, refer to the description of the register in the corresponding
section.
• The register states described here are for the basic operating modes. If there is a specific reset
for an on-chip peripheral module, refer to the section on that on-chip module.
Rev. 3.00 Jan. 18, 2008 Page 1237 of 1458
REJ09B0033-0300