SH7720 Datasheet, PDF (15/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

8.3.1 Interrupt Priority Registers A to J (IPRA to IPRJ)................................................ 247
8.3.2 Interrupt Control Register 0 (ICR0)...................................................................... 249
8.3.3 Interrupt Control Register 1 (ICR1)...................................................................... 250
8.3.4 Interrupt Request Register 0 (IRR0) ..................................................................... 252
8.3.5 Interrupt Request Register 1 (IRR1) ..................................................................... 253
8.3.6 Interrupt Request Register 2 (IRR2) ..................................................................... 254
8.3.7 Interrupt Request Register 3 (IRR3) ..................................................................... 255
8.3.8 Interrupt Request Register 4 (IRR4) ..................................................................... 256
8.3.9 Interrupt Request Register 5 (IRR5) ..................................................................... 257
8.3.10 Interrupt Request Register 6 (IRR6) ..................................................................... 259
8.3.11 Interrupt Request Register 7 (IRR7) ..................................................................... 260
8.3.12 Interrupt Request Register 8 (IRR8) ..................................................................... 261
8.3.13 Interrupt Request Register 9 (IRR9) ..................................................................... 262
8.3.14 PINT Interrupt Enable Register (PINTER)........................................................... 264
8.3.15 Interrupt Control Register 2 (ICR2)...................................................................... 265
8.4 Interrupt Sources................................................................................................................ 266
8.4.1 NMI Interrupt........................................................................................................ 266
8.4.2 IRQ Interrupts ....................................................................................................... 266
8.4.3 IRL interrupts........................................................................................................ 267
8.4.4 PINT Interrupts ..................................................................................................... 268
8.4.5 On-Chip Peripheral Module Interrupts ................................................................. 268
8.4.6 Interrupt Exception Handling and Priority............................................................ 269
8.5 Operation ........................................................................................................................... 276
8.5.1 Interrupt Sequence ................................................................................................ 276
8.5.2 Multiple Interrupts ................................................................................................ 278
Section 9 Bus State Controller (BSC)..................................................................279
9.1 Features.............................................................................................................................. 279
9.2 Input/Output Pins ............................................................................................................... 283
9.3 Area Overview ................................................................................................................... 285
9.3.1 Area Division........................................................................................................ 285
9.3.2 Shadow Area......................................................................................................... 285
9.3.3 Address Map ......................................................................................................... 287
9.3.4 Area 0 Memory Type and Memory Bus Width .................................................... 289
9.3.5 Data Alignment..................................................................................................... 289
9.4 Register Descriptions ......................................................................................................... 290
9.4.1 Common Control Register (CMNCR) .................................................................. 291
9.4.2 CSn Space Bus Control Register (CSnBCR) ........................................................ 294
9.4.3 CSn Space Wait Control Register (CSnWCR) ..................................................... 299
9.4.4 SDRAM Control Register (SDCR)....................................................................... 325
Rev. 3.00 Jan. 18, 2008 Page xv of lxii