SH7720 Datasheet, PDF (756/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
12
TDREQ 0
R
Transmit Data Transfer Request
0: Indicates that the size of empty space in the transmit
FIFO does not exceed the size specified by the TFWM
bit in SIFCTR.
1: Indicates that the size of empty space in the transmit
FIFO exceeds the size specified by the TFWM bit in
SIFCTR.
A transmit data transfer request is issued when the empty
space in the transmit FIFO exceeds the size specified by
the TFWM bit in SIFCTR.
When using transmit data transfer through the DMAC,
this bit is always cleared by one DMAC access. After
DMAC access, when conditions for setting this bit are
satisfied, the SIOF again indicates 1 for this bit.
• This bit is valid when the TXE bit in SICTR is 1.
• This bit indicates a state; if the size of empty space in
the transmit FIFO is less than the size specified by
the TFWM bit in SIFCTR, the SIOF clears this bit.
• If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
11

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10
RCRDY 0
R
Receive Control Data Ready
0: Indicates that the SIRCR stores no valid data.
1: Indicates that the SIRCR stores valid data.
• If SIRCR is written when this bit is set to 1, SIRCR is
modified by the latest data.
• This bit is valid when the RXE bit in SICTR is set to 1.
• This bit indicates a state of the SIOF. If SIRCR is
read, the SIOF clears this bit.
• If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
Rev. 3.00 Jan. 18, 2008 Page 694 of 1458
REJ09B0033-0300