SH7720 Datasheet, PDF (328/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
8.4 Interrupt Sources
There are four types of interrupt sources: NMI, IRQ, IRL, and on-chip peripheral modules. Each
interrupt has a priority level (0 to 16), with 1 the lowest and 16 the highest. Priority level 0 masks
an interrupt, so the interrupt request is ignored.
8.4.1 NMI Interrupt
The NMI interrupt has the highest priority level of 16. When the BLMSK bit in the interrupt
control register 1 (ICR1) is 1 or the BL bit in the status register (SR) is 0, NMI interrupts are
accepted if the MAI bit in ICR1 is 0. NMI interrupts are edge-detected. In sleep or standby mode,
the interrupt is accepted regardless of the BL setting. The NMI edge select bit (NMIE) in the
interrupt control register 0 (ICR0) is used to select either rising or falling edge detection.
When using edge-input detection for NMI interrupts, a pulse width of at least two Pφ cycles
(peripheral clock) is necessary. NMI interrupt exception handling does not affect the interrupt
mask bits (I3 to I0) in the status register (SR). When the BL bit is 1, only an NMI interrupt is
accepted if the BLMSK bit in ICR1 is 1.
It is possible to wake the chip up from sleep mode or standby mode with an NMI interrupt.
8.4.2 IRQ Interrupts
IRQ interrupts are input by level or edge from pins IRQ0 to IRQ5. The priority level can be set by
interrupt priority registers C and D (IPRC and IPRD) in a range from 0 to 15.
When using edge-sensing for IRQ interrupts, clear the interrupt source by having software read 1
from the corresponding bit in IRR0, then write 0 to the bit.
When ICR1 is rewritten, IRQ interrupts may be mistakenly detected, depending on the IRQ pin
states. To prevent this, rewrite the register while interrupts are masked, then release the mask after
clearing the illegal interrupt by reading the interrupt request register 0 (IRR0) and writing 0 to
IRR0.
Edge input interrupt detection requires input of a pulse width of more than two cycles on a Pφ
clock basis.
When using level-sensing for IRQ interrupts, the pin levels must be retained until the CPU
samples the pins. Therefore, the interrupt source must be cleared by the interrupt handler.
Rev. 3.00 Jan. 18, 2008 Page 266 of 1458
REJ09B0033-0300