SH7720 Datasheet, PDF (119/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Addressing
Mode
Register
indirect with
displacement
Instruction
Format
Effective Address Calculation Method
Calculation Formula
@(disp:4,
Rn)
Effective address is register Rn contents with 4-bit Byte: Rn + disp
displacement disp added. After disp is zero-
Word: Rn + disp × 2
extended, it is multiplied by 1 (byte), 2 (word), or 4
(longword), according to the operand size.
Longword: Rn + disp × 4
Rn
disp
+
(zero-extended)
×
Rn
+ disp × 1/2/4
Indexed
@(R0, Rn)
register indirect
GBR indirect with @(disp:8,
displacement GBR)
1/2/4
Effective address is sum of register Rn
and R0 contents.
Rn + R0
Rn
+
Rn + R0
R0
Effective address is register GBR contents with 8- Byte: GBR + disp
bit displacement disp added. After disp is zero- _{Word: GBR + disp × 2}
extended, it is multiplied by 1 (byte), 2 (word), or 4
(longword), according to the
Longword:
operand size.
GBR + disp × 4
GBR
disp
+
(Zero-extended)
×
GBR
+ disp × 1/2/4
Indexed GBR
indirect
1/2/4
@(R0, GBR) Effective address is sum of register GBR and R0 GBR + R0
contents.
GBR
+
GBR + R0
R0
Rev. 3.00 Jan. 18, 2008 Page 57 of 1458
REJ09B0033-0300