SH7720 Datasheet, PDF (1164/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 31 MultiMediaCard Interface (MMCIF)
[1]
[2]
No
Is FRDYI interrupt generated
or does DMA transfer end?
Yes
Write 1 to DATEN
Does DMA transfer ^No
end?
Yes
Set DMACR to H'00
No
Is DTI interrupt
generated?
Yes
Yes
Is CRCERI or WRERI
interrupt generated?
No
Yes
Is DTERI interrupt
generated?
No
No
Is DRPI interrupt
generated?
Yes
No
Is DTBUSY
detected?
Yes
No
Is DBSYI interrupt
generated?
Yes
Yes
Is next block
written?
No
Write 1 to CMDOFF
Write 1 to CMDOFF
Execute CMD12
Execute CMD12
Set DMACR to H'00
FIFO clear
Write 1 to CMDOFF
Command sequence end
Figure 31.29 Operational Flowchart for Write Sequence
(Open-ended Multiblock Transfer) (2)
Rev. 3.00 Jan. 18, 2008 Page 1102 of 1458
REJ09B0033-0300