SH7720 Datasheet, PDF (938/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 26 LCD Controller (LCDC)
26.3.6 LCDC Start Address Register for Lower Display Data Fetch (LDSARL)
When a DSTN panel is used, LDSARL specifies the fetch start address for the lower side of the
panel.
Bit
Bit Name Initial Value R/W
31 to 28 
All 0
R
27, 26 
All 1
R
25 to 4 SAL25 to All 0
R/W
SAL4
3 to 0 
All 0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
These bits are always read as 1. The write value
should always be 1.
Start Address for Lower Panel Display Data Fetch
The start address for data fetch of the display data
must be set within the synchronous DRAM area of
area 3.
STN and TFT: Cannot be used
DSTN: Start address for fetching display data
corresponding to the lower panel
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 3.00 Jan. 18, 2008 Page 876 of 1458
REJ09B0033-0300