SH7720 Datasheet, PDF (870/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 25 USB Function Controller (USBF)
25.3.1 Interrupt Flag Register 0 (IFR0)
IFR0 is an interrupt flag register for EP0i, EP0o, EP1, EP2, bus reset, and setup command
reception. When each flag is set to 1 and the interrupt is enabled in the corresponding bit of IER0,
an interrupt request is generated as specified by the corresponding bit in ISR0. Clearing is
performed by writing 0 to the bit to be cleared. Writing 1 is not valid and nothing is changed.
EP2 EMPTY and EP1 FULL are status bits that indicate the FIFO states of EP1 and EP2,
respectively. Therefore, EP2 EMPTY and EP1 FULL cannot be cleared.
Bit Bit Name Initial Value R/W Description
7
BRST
0
R/W Bus Reset
[Setting condition]
When a bus reset signal is detected on the USB bus.
[Clearing conditions]
• When reset
• When 0 is written to by CPU
6
EP1 FULL 0
R EP1 (Bulk-out) FIFO Full
[Setting condition]
The FIFO buffer of EP1 has a dual-buffer
configuration, and this bit is set when at least one of
the FIFO buffer is full.
[Setting conditions]
• When reset
• When both FIFO buffers are empty.
Note: EP1 FULL is a status bit, and cannot be
cleared.
5
EP2 TR 0
R/W EP2 (Bulk-in) Transfer Request
[Setting condition]
When an IN token is received from the host to EP2
and both of FIFO buffers are empty.
[Clearing conditions]
• When reset
• When 0 is written to by CPU
Rev. 3.00 Jan. 18, 2008 Page 808 of 1458
REJ09B0033-0300