SH7720 Datasheet, PDF (298/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 7 Exception Handling
• Example 2: Repeat loop consisting of three instructions
LDRS RptDtct + 4 ; [A]
LDRE RptDtct + 4 ; [A]
SETRC #4
; [A]
RptDtct: RptDtct
; [B] A repeat detection
instruction is an
instruction prior to a
repeat start instruction
RptStart: RptDtct1
; [C1][Repeat start instruction]
RptDtct2
; [C2]
RptEnd: RptDtct3
; [C2][Repeat end instruction]
instrNext
; [A]
• Example 3: Repeat loop consisting of two instructions
LDRS RptDtct + 6 ; [A]
LDRE RptDtct + 4 ; [A]
SETRC #4
; [A]
RptDtct: RptDtct
; [B] A repeat detection
instruction is an
instruction prior to a
repeat start instruction
RptStart: RptDtct1
; [C1][Repeat start instruction]
RptEnd: RptDtct2
; [C2][Repeat end instruction]
instrNext
; [A]
• Example 4: Repeat loop consisting of one instruction
LDRS RptDtct + 8 ; [A]
LDRE RptDtct + 4 ; [A]
SETRC #4
; [A]
RptDtct: RptDtct
; [B] A repeat detection
instruction is an
instruction prior to a
repeat start instruction
RptStart:
RptEnd: RptDtct1
; [C1][Repeat start
instruction]== [Repeat end
instruction]
instrNext
; [A]
Rev. 3.00 Jan. 18, 2008 Page 236 of 1458
REJ09B0033-0300