SH7720 Datasheet, PDF (1056/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 30 SIM Card Module (SIM)
Initial
Bit Bit Name Value R/W Description
1
CKE1
0
R/W Clock Enable 1, 0
0
CKE0
0
R/W Select the clock source for the smart card interface, and
enable/disable clock output from the SIM_CLK pin.
00: Fix the output pin at low
01: Clock output as the output pin
10: Fix the output pin at high
11: Clock output as the output pin
30.3.4 Transmit Shift Register (SCTSR)
SCTSR is a shift register that transmits serial data.
The smart card interface transfers transmit data from the transmit data register (SCTDR) to
SCTSR, and then sends the data in order from the LSB or MSB to the SIM_TXD pin to perform
serial data transmission.
When data transmission of one byte is completed, transmit data is automatically transferred from
SCTDR to SCTSR, and transmission is initiated. When the TDRE flag in the serial status register
(SCSSR) is set to 1, no data is transferred from SCTDR to SCTSR.
Direct reading and writing of SCTSR from the CPU or DMAC is not possible.
30.3.5 Transmit Data Register (SCTDR)
SCTDR is an 8-bit readable/writable register that stores data for serial transmission.
When the smart card interface detects a vacancy in the transmit shift register (SCTSR), transmit
data written to SCTDR is transferred to SCTSR, and serial transmission is initiated. During
SCTSR serial data transmission, if the next transmit data is written to SCTDR, continuous serial
transmission is possible.
Initial
Bit
Bit Name Value R/W Description
7 to 0 SCTD7 to All 1
SCTD0
R/W Transmit Data
Store data for serial transmission.
Rev. 3.00 Jan. 18, 2008 Page 994 of 1458
REJ09B0033-0300