SH7059 Datasheet, PDF (945/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

29.3.13 AUD Timing
Table 29.18 shows AUD timing.
Table 29.18 AUD Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,
PV_CC2 = 5.0 V ±0.5 V, AV_CC = 5.0 V ±0.5 V, AV_ref = 4.5 V to AV_CC,
V_SS = PLLV_SS = AV_SS = 0 V, T_a = –40°C to 125°C.
When PV_CC1 = 3.3 V ±0.3 V, V_CC = PV_CC1.
When writing or erasing on-chip flash memory, T_a = –40°C to 85°C.
Item
Symbol
Min
Max
AUDRST pulse width (Branch trace)
AUDRST pulse width (RAM monitor)
AUDMD setup time (Branch trace)
AUDMD setup time (RAM monitor)
Branch trace clock cycle
Branch trace clock duty
Branch trace data delay time
Branch trace data hold time
Branch trace SYNC delay time
Branch trace SYNC hold time
RAM monitor clock cycle
RAM monitor clock low pulse width
RAM monitor output data delay time
RAM monitor output data hold time
RAM monitor input data setup time
RAM monitor input data hold time
RAM monitor SYNC setup time
RAM monitor SYNC hold time
Load conditions: AUDCK (branch trace):
t_AUDRSTW
10
—
t
5
—
AUDRSTW
t_AUDMDS
10
—
t_AUDMDS
5
—
t_BTCYC
1
1
t_BTCKW
40
60
t_BTDD
—
40
t_BTDH
0
—
t_BTSD
—
40
t_BTSH
0
—
t_RMCYC
100
—
t_RMCKW
45
—
t_RMDD
7
t – _RMCYC 20
t_RMDHD
5
—
t_RMDS
20
—
t_RMDH
5
—
t_RMSS
20
—
t_RMSH
5
—
CL = 30 pF: otherwise CL = 100 pF
AUDSYNC:
CL = 100 pF
AUDATA3 to AUDATA0: CL = 100 pF
29. Electrical Characteristics
Unit
t_cyc
t
RMCYC
t_cyc
t_RMCYC
t_cyc
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figures
Figure 29.26
Figure 29.27
Figure 29.28
Rev.3.00 Mar. 12, 2008 Page 855 of 948
REJ09B0177-0300