SH7059 Datasheet, PDF (221/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Direct Memory Access Controller (DMAC)
Table 10.1 DMAC Registers
Channel Name
Abbr.
R/W Initial Value Address
Register Size Access Size
0
DMA source address SAR0
R/W Undefined H'FFFFECC0 32 bits
16, 32*²
register 0
DMA destination
address register 0
DAR0
R/W Undefined H'FFFFECC4 32 bits
16, 32*²
DMA transfer
count register 0
DMATCR0 R/W Undefined H'FFFFECC8 32 bits
16, 32*²
DMA channel control CHCR0
register 0
R/W*¹ H'00000000 H'FFFFECCC 32 bits
16, 32*²
1
DMA source address SAR1
R/W Undefined H'FFFFECD0 32 bits
16, 32*²
register 1
DMA destination
address register 1
DAR1
R/W Undefined H'FFFFECD4 32 bits
16, 32*²
DMA transfer
count register 1
DMATCR1 R/W Undefined H'FFFFECD8 32 bits
16, 32*³
DMA channel control CHCR1
register 1
R/W*¹ H'00000000 H'FFFFECDC 32 bits
16, 32*²
2
DMA source address SAR2
R/W Undefined H'FFFFECE0 32 bits
16, 32*²
register 2
DMA destination
address register 2
DAR2
R/W Undefined H'FFFFECE4 32 bits
16, 32*²
DMA transfer
count register 2
DMATCR2 R/W Undefined H'FFFFECE8 32 bits
16, 32*³
DMA channel control CHCR2
register 2
R/W*¹ H'00000000 H'FFFFECEC 32 bits
16, 32*²
3
DMA source address SAR3
R/W Undefined H'FFFFECF0 32 bits
16, 32*²
register 3
DMA destination
address register 3
DAR3
R/W Undefined H'FFFFECF4 32 bits
16, 32*²
DMA transfer
count register 3
DMATCR3 R/W Undefined H'FFFFECF8 32 bits
16, 32*³
DMA channel control CHCR3
register 3
R/W*¹ H'00000000 H'FFFFECFC 32 bits
16, 32*²
Shared DMA operation
DMAOR
R/W*¹ H'0000
H'FFFFECB0 16 bits
16*⁴
register
Notes: Word access to a register takes four cycles, and longword access eight cycles.
Do not attempt to access an empty address, as operation canot be guaranteed if this
is done.
1. Write 0 after reading 1 in bit 1 of CHCR0–CHCR3 and in bits 1 and 2 of DMAOR to clear flags. No other writes
are allowed.
2. For 16-bit access of SAR0–SAR3, DAR0–DAR3, and CHCR0–CHCR3, the 16-bit value on the side not
accessed is held.
3. DMATCR has a 24-bit configuration: bits 0–23. Writing to the upper 8 bits (bits 24–31) is invalid, and these bits
always read 0.
4. Do not use 32-bit access on DMAOR.
Rev.3.00 Mar. 12, 2008 Page 131 of 948
REJ09B0177-0300