SH7059 Datasheet, PDF (450/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Serial Communication Interface (SCI)
15.2.6 Serial Control Register (SCR)
Bit:
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The serial control register (SCR) operates the SCI transmitter/receiver, selects the serial clock output in asynchronous
mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read/write to
SCR. SCR is initialized to H'00 by a power-on reset and in hardware standby mode. The value is not retained in software
standby mode and it is initialized after release. It is not initialized by a manual reset.
• Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when
the transmit data register empty bit (TDRE) in the serial status register (SSR) is set to 1 by transfer of serial transmit
data from TDR to TSR.
Bit 7: TIE
0
1
Description
Transmit-data-empty interrupt request (TXI) is disabled
(Initial value)
The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then
clearing TDRE to 0, or by clearing TIE to 0.
Transmit-data-empty interrupt request (TXI) is enabled
• Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI) requested when the
receive data register full bit (RDRF) in the serial status register (SSR) is set to 1 by transfer of serial receive data from
RSR to RDR. It also enables or disables receive-error interrupt (ERI) requests.
Bit 6: RIE
0
1
Description
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled
(Initial value)
RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag (FER,
PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0.
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled
• Bit 5—Transmit Enable (TE): Enables or disables the SCI serial transmitter.
Bit 5: TE
0
1
Description
Transmitter disabled
(Initial value)
The transmit data register empty bit (TDRE) in the serial status register (SSR) is locked at 1.
Transmitter enabled
Serial transmission starts when the transmit data register empty (TDRE) bit in the serial
status register (SSR) is cleared to 0 after writing of transmit data into TDR. Select the
transmit format in SMR before setting TE to 1.
Rev.3.00 Mar. 12, 2008 Page 360 of 948
REJ09B0177-0300