SH7059 Datasheet, PDF (629/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20.1.3 Pin Configuration
Table 20.1 shows the H-UDI pin configuration.
Table 20.1 Pin Configuration
Pin Name
Test clock
Test mode select
Test data input
Test data output
Test reset
Abbreviation
TCK
TMS
TDI
TDO
TRST
20. High-performance User Debug Interface (H-UDI)
I/O
Input
Input
Input
Output
Input
Function
Test clock input
Test mode select input signal
Serial data input
Serial data output
Test reset input signal
20.1.4 Register Configuration
Table 20.2 shows the H-UDI registers.
Table 20.2 Register Configuration
Register
Abbreviation R/W*¹ Initial Value*²
Address
Access Size
(Bits)
Instruction register
SDIR
R
H'E000
H'FFFFF7C0
8/16/32
Status register
SDSR
R/W
H'5001 (SH7058SF)
H'FFFFF7C2
8/16/32
H'0F01 (SH7059F)
Data register H
SDDRH
R/W
Undefined
H'FFFFF7C4
8/16/32
Data register L
SDDRL
R/W
Undefined
H'FFFFF7C6
8/16/32
Bypass register
SDBPR
—
—
—
—
Boundary scan register SDBSR
—
—
—
—
ID code register
SDIDR
—
H'08016447 (SH7058SF) —
—
H'0800B447 (SH7059F)
Notes: 1. Indicates whether the register can be read from/written to by the CPU.
2. Initial value when the TRST signal is input. Registers are not initialized by a reset (power-on or manual).
Instructions and data can be input to the instruction register (SDIR) and data register (SDDR) by serial transfer from the
test data input pin (TDI). Data from SDIR, the status register (SDSR), and SDDR can be output via the test data output pin
(TDO). The bypass register (SDBPR) is a 1-bit register to which TDI and TDO are connected in BYPASS, CLAMP, or
HIGHZ mode. The boundary scan register (SDBSR) is a 474-bit register, and is connected to TDI and TDO in the
SAMPLE/PRELOAD or EXTEST mode. The ID code register (SDIDR) is a 32-bit register; a fixed code can be output via
TDO in the IDCODE mode. All registers, except SDBPR, SDBSR, and SDIDR, can be accessed from the CPU.
Rev.3.00 Mar. 12, 2008 Page 539 of 948
REJ09B0177-0300