SH7059 Datasheet, PDF (620/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Multi-Trigger A/D Converter (MTAD)
2. When conversion of the first channel (AN0) is completed, the result is transferred to ADDR0.
3. Conversion proceeds in the same way through the eighth channel (AN7).
4. When conversion is completed for all the selected channels (AN0 to AN7), the ADF flag is set to 1. If the ADIE bit is
1 at the completion of conversion, an ADI interrupt is requested after A/D conversion ends.
5. If the A/D counter (ADCNT) and A/D general register (ADGR) values match during conversion of AN0 to AN7, the
multi-trigger A/D conversion on the channels for which the conversion has been requested is started after A/D
conversion of the current channel ends.
6. When the multi-trigger A/D conversion on the channels for which the conversion has been requested is completed, the
result is transferred to ADDRx and the A/D data select (ADSELx) is inverted. If the TADIExA or TADIExB is 1 at
the completion of multi-trigger A/D conversion, a TADIA or TADIB interrupt of the completed channel is requested.
7. After step 6, the A/D conversion starts again on the channel that has been halted. While ADST is 1, steps 2 to 7 are
repeated.
Note: When multi-trigger A/D conversion is requested simultaneously from two sources, conversion is performed
according to the priority.
Priority high
Priority low
CMFxA
>
CMFxB
Rev.3.00 Mar. 12, 2008 Page 530 of 948
REJ09B0177-0300