SH7059 Datasheet, PDF (489/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Synchronous Serial Communication Unit (SSU)
16.2 Input/Output Pins
Table 16.1 shows the SSU pin configuration.
Table 16.1 Pin Configuration
Name
Pin Name*
I/O
Function
0
SSCK0
O
SSU clock output of channel 0
SSI0
I
SSU data input of channel 0
SSO0
O
SCS0
I/O
SSU data output of channel 0
SSU chip select input/output of channel 0
1
SSCK1
O
SSU clock output of channel 1
SSI1
I
SSU data input of channel 1
SSO1
O
SSU data output of channel 1
SCS1
I/O
SSU chip select input/output of channel 1
Note: * Channel numbers are omitted. Pin names in this section are written as follows: SSCK, SSI, SSO, and SCS.
16.3 Register Descriptions
The SSU has the following registers.
(1) Channel 0
• SS control register H_0 (SSCRH_0)
• SS control register L_0 (SSCRL_0)
• SS mode register_0 (SSMR_0)
• SS enable register_0 (SSER_0)
• SS status register_0 (SSSR_0)
• SS transmit data register 0_0 (SSTDR0_0)
• SS transmit data register 1_0 (SSTDR1_0)
• SS transmit data register 2_0 (SSTDR2_0)
• SS transmit data register 3_0 (SSTDR3_0)
• SS receive data register 0_0 (SSRDR0_0)
• SS receive data register 1_0 (SSRDR1_0)
• SS receive data register 2_0 (SSRDR2_0)
• SS receive data register 3_0 (SSRDR3_0)
• SS shift register _0 (SSTRSR_0)
(2) Channel 1
• SS control register H_1 (SSCRH_1)
• SS control register L_1 (SSCRL_1)
• SS mode register_1 (SSMR_1)
• SS enable register_1 (SSER_1)
• SS status register_1 (SSSR_1)
• SS transmit data register 0_1 (SSTDR0_1)
• SS transmit data register 1_1 (SSTDR1_1)
• SS transmit data register 2_1 (SSTDR2_1)
Rev.3.00 Mar. 12, 2008 Page 399 of 948
REJ09B0177-0300