SH7059 Datasheet, PDF (512/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
The following features have been added in the HCAN-II.
• IRR0 function to notify a software reset and halt
• Halt mode status bit and error passive status bit added to GSR
• Timestamp support of all incoming messages and outgoing messages
• Supports various test modes
• Data frame and remote frame are separated (IRR2 is independent from IRR1 and RXPR from RFRR)
• When transmitting, the highest priority search is scanned from mailbox 31 down to mailbox 1
• When receiving, the matching ID search is scanned from mailbox 31 down to mailbox 0, and one received message is
only stored into one mailbox
• More flexible BCR
• Bus off/bus off recover interrupt (IRR6)
Others:
• HCAN-II connection method: Two connections are available
32-buffer HCAN-II • 2 channels (transmit pin • 2 and receive pin • 2)
64-buffer HCAN-II (wire AND) • 1 channel (transmit pin • 1 and receive pin • 1)
• DMAC can be activated by a receive message of a mailbox (only mailbox 0 in HCAN0)
Rev.3.00 Mar. 12, 2008 Page 422 of 948
REJ09B0177-0300