SH7059 Datasheet, PDF (265/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
Block Diagram of Channels 6 and 7: Figure 11.6 shows a block diagram of ATU-II channels 6 and 7.
STR6×, 7×
Prescaler 2
TO6A
TO6B
TO6C
TO6D
Clock selection
logic (A–D
independent)
BFR6A
CYLR6A
DTR6A
TCNT6A
BFR6B
CYLR6B
DTR6B
TCNT6B
BFR6C
CYLR6C
DTR6C
TCNT6C
BFR6D
CYLR6D
DTR6D
TCNT6D
TCR6A
TCR6B
TSR6
TIER6
PMDR
Compa-
rator
Control
logic
I/O control
Compare-match
interrupts × 4
Internal data bus and address bus
Note: Channel 7 has no PMDR7.
Figure 11.6 Block Diagram of Channel 6 (Same Configuration for Channel 7)
Rev.3.00 Mar. 12, 2008 Page 175 of 948
REJ09B0177-0300