SH7059 Datasheet, PDF (35/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
21.3.13 Port F Control Registers H and L (PFCRH,
PFCRL)
771, 772
PFCRH and PFCRL are initialized to H'0015 and H'5000,
respectively, by a power-on reset (excluding a WDT
power-on reset), and in hardware standby mode. They are
not initialized in software standby mode or sleep mode.
Bit: 15
14
13
12
11
CKHIZ PF15MD — PF14MD —
Initial value: 0
0
0
0
0
R/W: R/W R/W
R
R/W
R
8
PF12MD
0
R/W
SH7058S/SH7059
22.3.13 Port F Control Registers H and L (PFCRH,
PFCRL)
Description amended
PFCRH and PFCRL are initialized to H'0015 and H'5000,
respectively, by a power-on reset (excluding a WDT
power-on reset), in hardware standby mode, and in
software standby mode. They are not initialized in sleep
mode.
Bit:
Initial value:
R/W:
15
14
13
12
11
CKHIZ PF15MD PF15MD PF14MD PF14MD
0
1
0
1
0
0
0
0
0
R/W R/W R/W R/W R/W
8
PF12MD
0
R/W
• Bit 14—PF15 Mode Bit (PF15MD): Selects the function
of pin PF15/BREQ.
Bit 14: PF15MD
0
1
Expanded Mode
General input/output (PF15)
(Initial value)
Bus request input (BREQ )
Description
Single-Chip Mode
General input/output (PF15)
(Initial value)
General input/output (PF15)
• Bits 14 and 13—PF15 Mode Bit 0, 1 (PF15MD0,
PF15MD1): Selects the function of pin
PF15/BREQ/SCS1.
Bit 14: PF15MD0
0
1
Bit 13: PF15MD1
0
1
0
1
Expanded Mode
General input/output (PF15)
(Initial value)
Reserved (Do not set)
Bus request input (BREQ)
Reserved (Do not set)
Description
Single-Chip Mode
General input/output (PF15)
(Initial value)
Chip select input/output (SCS1)
General input/output (PF15)
• Bit 13—Reserved: This bit is always read as 0. The
write value should always be 0.
• Bit 12—PF14 Mode Bit (PF14MD): Selects the function
of pin PF14/BACK.
Bit 12: PF14MD
0
1
Description
Expanded Mode
Single-Chip Mode
General input/output (PF14)
(Initial value)
General input/output (PF14)
(Initial value)
Bus acknowledge output (BACK) General input/output (PF14)
• Bits 12 and 11—PF14 Mode Bit 0,1(PF14MD0,
PF14MD1): Selects the function of pin
PF14/BACK/SCS0.
Bit 12: PF14MD0
0
1
Bit 11: PF14MD1
0
1
0
1
Description
Expanded Mode
Single-Chip Mode
General input/output (PF14)
(Initial value)
General input/output (PF14)
(Initial value)
Reserved (Do not set)
Chip select input/output (SCS0)
Bus acknowledge output (BACK) General input/output (PF14)
Reserved (Do not set)
• Bit 11—Reserved: This bit is always read as 0. The
write value should always be 0.
21.3.14 Port G IO Register (PGIOR)
776
PGIOR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode
or sleep mode.
21.3.15 Port G Control Register (PGCR)
777
PGCR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode
or sleep mode.
22.3.14 Port G IO Register (PGIOR)
Description amended
PGIOR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), in hardware standby
mode, in software standby mode. It is not initialized in .
sleep mode.
22.3.15 Port G Control Register (PGCR)
Description amended
PGCR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), in hardware standby
mode, and in software standby mode. It is not initialized in
sleep mode.
Rev.3.00 Mar. 12, 2008 Page xxxv of xc
REJ09B0177-0300