SH7059 Datasheet, PDF (228/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Direct Memory Access Controller (DMAC)
• Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA transfer. If this bit is set
during a data transfer, transfers on all channels are suspended. The CPU cannot write a 1 to the AE bit. Clearing is
effected by a 0 write after a 1 read.
Bit 2: AE
0
1
Description
No address error, DMA transfer enabled
[Clearing condition]
Write AE = 0 after reading AE = 1
Address error, DMA transfer disabled
[Setting condition]
Address error due to DMAC
(Initial value)
• Bit 1—NMI Flag (NMIF): Indicates input of an NMI. This bit is set irrespective of whether the DMAC is operating or
suspended. If this bit is set during a data transfer, transfers on all channels are suspended. The CPU is unable to write a
1 to the NMIF. Clearing is effected by a 0 write after a 1 read.
Bit 1: NMIF
0
1
Description
No NMI interrupt, DMA transfer enabled
[Clearing condition]
Write NMIF = 0 after reading NMIF = 1
NMI has occurred, DMC transfer disabled
[Setting condition]
NMI interrupt occurrence
(Initial value)
• Bit 0—DMAC Master Enable (DME): This bit enables activation of the entire DMAC. When the DME bit and DE bit
of the CHCR register for the corresponding channel are set to 1, that channel is transfer-enabled. If this bit is cleared
during a data transfer, transfers on all channels are suspended.
Even when the DME bit is set, when the TE bit of CHCR is 1, or its DE bit is 0, transfer is disabled if the NMIF or AE
bit in DMAOR is set to 1.
Bit 0: DME
0
1
Description
Operation disabled on all channels
Operation enabled on all channels
(Initial value)
10.3 Operation
When there is a DMA transfer request, the DMAC starts the transfer according to the channel priority order; when the
transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in two modes: auto-request and on-
chip peripheral module request. Transfer is performed only in dual address mode, and either direct or indirect address
transfer mode can be used. The bus mode can be either burst or cycle-steal.
10.3.1 DMA Transfer Flow
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count register
(DMATCR), DMA channel control registers (CHCR), and DMA operation register (DMAOR) are set to the desired
transfer conditions, the DMAC transfers data according to the following procedure:
Rev.3.00 Mar. 12, 2008 Page 138 of 948
REJ09B0177-0300