SH7059 Datasheet, PDF (44/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
23.5.2 User Program Mode
(1) On-Chip RAM Address Map when
Programming/Erasing is Executed
Figure 23.10 RAM Map after Download
869
Area to be downloaded (Size: 2 kbytes)
Address
FTDAR setting+2048
(2.3) VBR is cleared to 0 and 1 is written to the SCO bit of
FCCS, and then download is executed.
871
When download is executed, particular interrupt
processing, which is accompanied by the bank switch as
described below, is performed as an internal
microcomputer processing, so VBR need to be cleared to
0. Four NOP instructions are executed immediately after
the instructions that set the SCO bit to 1.
(4) Erasing and Programming Procedure in User Program
Mode
Figure 23.13 Sample Procedure of Repeating RAM
Emulation, Erasing, and Programming (Overview)
877
Set FTDAR to H'03
(Specify H'FFFF1800 as download destination)
SH7058S/SH7059
24.5.2 User Program Mode
(1) On-Chip RAM Address Map when
Programming/Erasing is Executed
Figure 24.10 RAM Map after Download
Figure amended
Area to be downloaded (Size: 3 Kbytes)
Address
FTDAR setting+3072
(2.3) VBR is cleared to 0 and 1 is written to the SCO bit of
FCCS, and then download is executed.
Description amended
When download is executed, particular interrupt
processing, which is accompanied by the bank switch as
described below, is performed as an internal
microcomputer processing, so VBR need to be cleared to
0. Eight NOP instructions are executed immediately after
the instructions that set the SCO bit to 1.
(4) Erasing and Programming Procedure in User Program
Mode
Figure 24.13 Sample Procedure of Repeating RAM
Emulation, Erasing, and Programming (Overview)
Figure amended
Set FTDAR to H'04
(Specify H'FFFF2000 as download destination)
• Be sure to initialize both the erasing program and
programming program.
Initialization by setting the FPEFEQ and FUBRA
parameters must be performed for both the erasing
program and the programming program. Initialization must
be executed for both entry addresses: (download start
address for erasing program) + 32 bytes (H'FFFF1020 in
this example) and (download start address for
programming program) + 32 bytes (H'FFFF1820 in this
example).
23.5.3 User Boot Mode
(1) User Boot Mode Initiation
878
… When the reset start is executed in user boot mode, the
check routine for flash-memory related registers runs. The
RAM area about 1.2 kbytes from H'FFFF0800 and 4 bytes
from H'FFFFBFFC (a stack area) is used by the routine.
While the check routine is running, NMI and all other
interrupts cannot be accepted. Neither can the AUD be
used in this period. This period is 100 μs while operating at
an internal frequency of 40 MHz.
Description amended
• Be sure to initialize both the erasing program and
programming program.
Initialization by setting the FPEFEQ and FUBRA
parameters must be performed for both the erasing
program and the programming program. Initialization must
be executed for both entry addresses: (download start
address for erasing program) + 32 bytes (H'FFFF1020 in
this example) and (download start address for
programming program) + 32 bytes (H'FFFF2020 in this
example).
24.5.3 User Boot Mode
(1) User Boot Mode Initiation
Description amended
… When the reset start is executed in user boot mode, the
check routine for flash-memory related registers runs. The
RAM area about 3 Kbytes from H'FFFFB000 and 128 bytes
from H'FFFFBF80 to H'FFFFBFFF (a stack area) is used
by the routine. While the check routine is running, NMI and
all other interrupts cannot be accepted. Neither can the
AUD be used in this period. This period is 100 μs while
operating at an internal frequency of 80 MHz.
Rev.3.00 Mar. 12, 2008 Page xliv of xc
REJ09B0177-0300