SH7059 Datasheet, PDF (275/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
• Bits 7 to 1—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 0—Counter Start 11 (STR11): Starts and stops free-running counter 11 (TCNT11).
Bit 0: STR11
0
1
Description
TCNT11 is halted
TCNT11 counts
(Initial value)
11.2.2 Prescaler Registers (PSCR)
The prescaler registers (PSCR) are 8-bit registers. The ATU-II has four PSCR registers.
Channel
0, 1, 2, 3, 4, 5, 8, 11
6
7
10
Abbreviation
PSCR1
PSCR2
PSCR3
PSCR4
Function
Prescaler setting for respective channels
PSCRx is an 8-bit writable register that enables the first-stage counter clock φ' input to each channel to be set to any value
from Pφ/1 to Pφ/32.
Bit:
7
6
5
4
3
2
1
0
—
—
—
PSCxE PSCxD PSCxC PSCxB PSCxA
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R/W
R/W
R/W
R/W
Note: x = 1 to 4
Input counter clock φ' is determined by setting PSCxA to PSCxE: φ' is Pφ/1 when the set value is H'00, and Pφ/32 when
H'1F.
PSCRx is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode.
The internal clock φ' set with this register can undergo further second-stage scaling to create clock φ" for channels 1 to 8
and 11, the setting being made in the timer control register (TCR).
• Bits 7 to 5—Reserved: These bits cannot be modified.
• Bits 4 to 0—Prescaler (PSCxE, PSCxD, PSCxC, PSCxB, PSCxA): These bits specify frequency division of first-stage
counter clock φ' input to the corresponding channel.
Rev.3.00 Mar. 12, 2008 Page 185 of 948
REJ09B0177-0300