SH7059 Datasheet, PDF (441/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Compare Match Timer (CMT)
14.5 Usage Notes
Take care that the contentions described in sections 14.5.1 to 14.5.3 do not arise during CMT operation.
14.5.1 Contention between CMCNT Write and Compare Match
If a compare match signal is generated during the T2 state of the CMCNT counter write cycle, the CMCNT counter clear
has priority, so the write to the CMCNT counter is not performed. Figure 14.6 shows the timing.
CMCNT write cycle
T1
T2
Pφ
Address
CMCNT
Internal
write signal
Compare
match signal
CMCNT
N
H'0000
Figure 14.6 CMCNT Write and Compare Match Contention
14.5.2 Contention between CMCNT Word Write and Incrementation
If an increment occurs during the T2 state of the CMCNT counter word write cycle, the counter write has priority, so no
increment occurs. Figure 14.7 shows the timing.
CMCNT write cycle
T1
T2
Pφ
Address
CMCNT
Internal
write signal
CMCNT input
clock
CMCNT
N
M
CMCNT write data
Figure 14.7 CMCNT Word Write and Increment Contention
Rev.3.00 Mar. 12, 2008 Page 351 of 948
REJ09B0177-0300